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Patkar, “A system and method for emulating a logic circuit design using programmable logic devices”, Patent Application No. Desai, Himanshu Sharma, Mitra Purandare and Sachin B. Location is bit far but hotel is very good Sachin Angral Location is but outside but OYO 14225 Bahl Regency. It’s newly built OYO 14225 Bahl Regency everything provide is neat and clean and room are good and clean.Department of Electrical Engineering IIT Bombay, Powai Mumbai 400 076, India Email : patkar[AT]Phone (Internal(O)) : (0091 22) - 2576-7490 Phone (Internal(R)) : 8490 Office room no: 231-C Fax: (0091 22) - 25723707 Publications C-[73] Vinay BY Kumar, Deval Shah, Mandar Datar and Sachin B Patkar, “Lightweight Forth Programmable No Cs” in 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), 2018, pp 368-373 J-[72] H. Patkar, “Matroids”, in Handbook of Graph Theory, Combinatorial Optimization, and Algorithms, Editor-in-Chief K. 2014, Seoul, South Korea 2014 C-[63] V Kumar, VBY Kumar, SB Patkar : FPGA-based implementation of M4RM for matrix multiplication over GF (2), VLSI Design and Test, 18th International Symposium on, 1-2, Banglore, 2014 C-[62] J Porwal, S Diwale, VBY Kumar, SB Patkar : Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems, VLSI Design, Automation and Test (VLSI-DAT), 2014 (IEEE) International Symposium on , 28-30 April 2014, Hsinchu city, Taiwan C-[61] H Sharma, S Sivasubramanian, S Patkar : Optimal communication scheduling for iterative decoding of irregular codes, Communications (NCC), 2014 Twentieth National Conference on, pp. 28 2014-March 2 2014, Kanpur, India, 2014 C-[60] Jasveer Singh T Jethra, Sachin B Patkar, Shamik Datta: Remote Triggered FPGA based Automated System, 11th International Conference on Remote Engineering and Virtual Instrumentation (REV), 309 - 314, Porto, Portugal, 26-28 Feb. Patkar, “Hardware –Software Scalable Architectures for Gaussian Elimination over GF(2) and higher Galois Fields” to appear in Proceedings of PECCS 2013, Barcelona. For further information, including about cookie settings, please read our Cookie Policy .By continuing to use this site, you consent to the use of cookies.Patkar, Mahesh Patil, Narendra N., Samir Shelke, Abhishek Kamath, and Debapratim Ghosh, “e-prayog: A New Paradigm for Electronics Laboratories”, IEEE International Conference on Technology Enhanced Education (ICTEE 2012), 2012 J-[49] Yogesh Dilip Save, H. Patkar, “Solution of Partial Differential Equations by electrical analogy”, (Elsevier) Journal of Computational Science 2 (2011) 18–30 C-[48] Subhasis Das and Sachin Patkar, “A Compact Gaussian Random Number Generator for Small Word Lengths”, Applied Reconfigurable Computing - 2011 (ARC-2011), Belfast, Ireland, 23-25 March 2011 C-[47] Sumedh Attarde, Siddharth Joshi, Yash Deshpande, Sunil Puranik and Sachin Patkar, “Double Precision Sparse Matrix Vector Multiplication Accelerator on FPGA”, PECCS-2010 (Pervasive and Embedded Computing and Communications Systems - 2011) C-[46] Balwinder Kumar, Yogesh Dilip Save, H. Patkar, “A Simple Relaxation based Circuit Simulator for VLSI Circuits with Emerging Devices”, CSC, 2011 (The 2011 International Conference on Scientific Computing), USA, 2011 C-[45] Hrishikesh Sharma, Subhasis Das, Rewati Raman Raut and Sachin Patkar, “HIGH THROUGHPUT MEMORY-EFFICIENT VLSI DESIGNS FOR STRUCTURED LDPC DECODING”, PECCS-2010 (Pervasive and Embedded Computing and Communications Systems - 2011) J-[44] B.

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Patkar: “A Design Methodology for Optimally Folded, Pipelined Architectures in VLSI Applications using Projective Space Lattices”, accepted for publication in Elsevier Journal of Microprocessors and Microsystems 37 (6), 674-683, 2013 J-[57] Yogesh Dilip Save, H. Patkar, “Solution of PDEs-Electrically Coupled Systems with Electrical Analogy.” Integration, the VLSI Journal 46 (4), 427-440, 2013 C-[56] Prateek Saxena, Vinay B. Patkar, and Dinesh Sharma: “An Affordable on-site and Remote Laboratory Solution for a Course in Modern Digital Design”, accepted for publication in IEEE EDUCON, Berlin 13th-17th March 2013. Patkar, “FPGA Implementation of particle filter based object tracking in video”, 3rd International Symposium on Electronic System Design (ISED), Kolkata, 19th-22nd December 2012. Patkar, Rajbabu Velmurugan, and Preeti Rao, “A Remote Lab For Real-Time Digital Signal Processing”, EDERC2012: 5th European DSP Education and Research Conference, 13- 14 September 2012, Amsterdam, Netherlands C-[51] Yogesh Dilip Save, H. Patkar, “Two Graph based cicuitsimulator for PDE –Electrical Analogy”, 25th Intl. Patkar, System for Error Control Coding using Expander-like codes constructed from higher dimensional Projective Spaces, and their Applications, Indian Patent Requested (2010), 2455/MUM/2010, (78 pages) C-[43] Swadesh Choudhary, Tejas Hiremani, Hrishikesh Sharma and Sachin Patkar, “A Folding Strategy for DFGs derived from Projective Geometry based graphs”, The 2010 International Congress on Computer Applications and Computational Science (CACS 2010), Singapore, Dec 4-6, 2010 C-[42] Subhendu Roy, Yogesh Dilip Save, H. Patkar, “Large Scale VLSI Circuit Simulation Using Point Relaxation”, CSC, 2010 (The 2010 International Conference on Scientific Computing), July 12-15, USA, 2010 J-[41] V.

in proceedings of International Conference on VLSI Design, 2012 C-[50] Madhumita Date, Sachin B.

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